ALTERA Design Processor Utilization Report                            scdec.rpt 
@(#) FIT Version 5.03    2/12/88 00:32:39 39.16
 ***** Design implemented successfully 
 
H. Hufenbecher (DL6NAD)
  January  5, 1992
SCDEC.SCH       Bild 2  
1.5
I/O-Decoder fuer Universal-SCIF              - NETLIST created by OrCAD/SDT
Input files : scdec.sdf 
ADP Options: Minimization = Yes,  Inversion Control = No,  LEF Analysis = No

OPTIONS: TURBO = OFF, SECURITY = OFF

               EP320 
             - - - - -
       SA9 -|1      20|- Vcc 
       SA8 -|2      19|- BUFEN\ 
       SA7 -|3      18|- ADCS\ 
   SA6_AEN -|4      17|- ADCRDY 
       SA5 -|5      16|- BIOW\ 
       SA4 -|6      15|- IOCS\ 
       SA3 -|7      14|- WAIT\ 
       SA2 -|8      13|- LOAD\ 
        QH -|9      12|- IORDY 
       GND -|10     11|- BIOR\ 
             - - - - -
                                                                     scdec.rpt 
**OUTPUTS** 

      Name  Pin  Resource  MCell  PTerms  | Sync Clock
 
     ADCS\   18      CONF      2    1/ 8  |     -     
    BUFEN\   19      CONF      1    3/ 8  |     -     
     IOCS\   15      CONF      5    1/ 8  |     -     
     IORDY   12      CONF      8    1/ 8  |     -     
     LOAD\   13      CONF      7    3/ 8  |     -     
     WAIT\   14      COIF      6    6/ 8  |     -     

 
**INPUTS** 

      Name  Pin  Resource  MCell  PTerms  | Sync Clock
 
    ADCRDY   17       INP      3    0/ 8  |     -     
     BIOR\   11       INP      -     -    |     -     
     BIOW\   16       INP      4    0/ 8  |     -     
        QH    9       INP      -     -    |     -     
       SA2    8       INP      -     -    |     -     
       SA3    7       INP      -     -    |     -     
       SA4    6       INP      -     -    |     -     
       SA5    5       INP      -     -    |     -     
   SA6_AEN    4       INP      -     -    |     -     
       SA7    3       INP      -     -    |     -     
       SA8    2       INP      -     -    |     -     
       SA9    1       INP      -     -    |     -     

 
**PART UTILIZATION**
 
 6/ 6  MacroCells (100%)
12/12  Input Pins (100%)
       PTerms Used 31%
Macrocell Interconnection Cross Reference                            scdec.rpt 

FEEDBACKS:                         
                       M M M M M M 
                       1 2 5 6 7 8 
BUFEN\ ... CONF @M1 -> . . . . . . @19
ADCS\ .... CONF @M2 -> . . . . . . @18
IOCS\ .... CONF @M5 -> . . . . . . @15
WAIT\ .... COIF @M6 -> . . . . . * @14
LOAD\ .... CONF @M7 -> . . . . . . @13
IORDY .... CONF @M8 -> . . . . . . @12


INPUTS:
 
SA9 ...... INP  @1  -> * * * * * .
SA8 ...... INP  @2  -> * * * * * .
SA7 ...... INP  @3  -> * * * * * .
SA6_AEN .. INP  @4  -> * * * * * .
SA5 ...... INP  @5  -> * * * * * .
SA4 ...... INP  @6  -> * * * * * .
SA3 ...... INP  @7  -> * * * * * .
SA2 ...... INP  @8  -> * . * * * .
QH ....... INP  @9  -> . . . * . .
BIOR\ .... INP  @11 -> . . . * . .
BIOW\ .... INP  @16 -> * . . * * . M4 
ADCRDY ... INP  @17 -> . . . * . . M3 
                       B A I W L I 
                       U D O A O O 
                       F C C I A R 
                       E S S T D D 
                       N \ \ \ \ Y 
                       \